用於平行渦輪碼之無衝突演算法

Abstract

在此論文中我們利用退火模擬演算法(Simulated Annealing Algorithm)提出無衝突演算法去解決平行渦輪碼中記憶體碰撞問題。再者，對於平行渦輪碼中的非本質記憶體，我們提出有效使記憶體面積減少的兩種架構； 其中一種架構是由平行單埠記憶體與一個緩衝暫存器所組成去取代原來須兩埠或雙埠記憶體所組成的架構。另外一個架構，我們基於前一個架構上再加上一個非本質函數的非線性映對器。在前兩種架構相較於傳統使用雙埠記憶體在 0.13 CMOS 聯電製程環境底下分別可以節省約 37 和 46 百分比記憶體使用量。

In this thesis, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories. And the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-μm CMOS process.