具輕摻雜汲極結構之多晶矽薄膜電晶體之溫度效應研究

Abstract

多晶矽薄膜電晶體在面板技術的應用上，由於具有高遷移率，有機會整合面板周邊電路，實現系統面板（System on Panel）的目標。而在實際的應用上，多晶矽薄膜電晶體通常會使用輕摻雜汲極結構。在本論文中，我們將分別針對多晶矽薄膜電晶體的載子遷移率，以及輕摻雜汲極區域所造成的寄生電阻效應，做相關的實驗分析與研究，尤其著重於遷移率與寄生電阻的溫度效應。

首先，我們提出一個遷移率模型，此模型是以熱電子發射效應以及聲子散射效應交互作用後所產生之溫度效應作為理論基礎來建構。我們利用該遷移率模型，針對無輕摻雜汲極結構的元件進行載子遷移率的模擬。而不論是在遷移率的模擬或是在元件電流特性的模擬中，都可以在不同的閘極偏壓與不同的環境溫度之下，分別得到與遷移率萃取值以及元件電流測量值相當吻合的結果。

接下來，我們討論了輕摻雜汲極結構所造成的寄生電阻效應。針對具輕摻雜汲極結構的元件，我們先由其電流特性計算出元件電阻，再以無輕摻雜汲極結構元件的電阻作為參考電阻，將其電阻相減，即可得到輕摻雜汲極區域所造成的寄生電阻。而根據由此萃取出的寄生電阻結果，我們發現寄生電阻會受到閘極偏壓的調變，而且對越短的輕摻雜汲極長度而言，其寄生電阻受到閘極偏壓調變的情形會越嚴重。

接著，我們利用 Silvaco 元件模擬軟體，針對具輕摻雜汲極的元件結構進行元件模擬的工作。根據元件模擬的結果，可以推論出在閘極電極的周圍，存在一個寄生電晶體，並且在溫度效應上，同樣受到熱電子發射效應的影響。此外，在距離閘極電極較遠的輕摻雜汲極區域，並不受到閘極偏壓的調變，因此在同一溫度下可視為定電阻，而在合理的推論下，我們認為此段未受閘極偏壓調變之輕摻雜汲極區域電阻，其溫度效應是由雜質散射效應所主導。

最後，我們根據上述的假設與分析，針對具輕摻雜汲極結構的元件，提出了一個包含溫度效應的寄生電阻模型，並且利用此寄生電阻模型，針對具輕摻雜汲極結構的元件進行寄生電阻的模擬。而不論是在寄生電阻的模擬或是在元件電流特性的模擬中，都可以在不同的閘極偏壓與不同的環境溫度之下，分別得到與寄生電阻萃取值以及元件電流測量值相當吻合的結果。

Polycrystalline silicon thin film transistors (Poly-Si TFTs) have been studied extensively for their application on system-on-panel (SOP) technology due to the high mobility. For actual applications, lightly-doped drain (LDD) structure is usually applied to Poly-Si TFTs. In this thesis, we will study on the effect of field effect mobility and parasitic resistance caused by LDD structure in Poly-Si TFTs, especially on the temperature response of field effect mobility and parasitic resistance.

First, the mobility modeling of the Poly-Si TFT without LDD structure is performed by using the proposed mobility model. The proposed mobility model has taken thermionic emission effect and phonon scattering effect into account to explain the temperature response of field effect mobility. Excellent agreement between experimental and modeling results over the wide range of gate voltage and temperature is both obtained in the field effect mobility modeling and the transfer characteristics modeling by using the proposed mobility model for the Poly-Si TFT without LDD structure.

Next, the parasitic resistance effect due to LDD structure is discussed. The parasitic resistance caused by LDD structure is calculated by subtracting the device resistance of the Poly-Si TFT without LDD structure from the device resistance of the Poly-Si TFTs with LDD structure. According to the extracted parasitic resistance data, it is found that the parasitic resistance is modulated by gate bias and the modulation is more serious for the Poly-Si TFTs with shorter LDD lengths.

After that, the device simulation results which are performed by Silvaco TCAD for the device with LDD structure show that parasitic transistor effect exists alongside the gate electrode. The parasitic transistor is also dominated by thermionic emission effect in temperature response. Besides, the resistance is treated as a pure resistor with a constant resistance at some temperature for the LDD region without gate bias modulation, and the mechanism of the temperature response in this series resistance region is preferred to conceive as impurity scattering effect.

Finally, the proposed parasitic resistance model is established basing on the analysis and the assumptions mentioned above. Good agreement between experimental and modeling results over the wide range of gate voltage and temperature is both obtained in the parasitic resistance modeling and the transfer characteristics modeling by using the proposed parasitic resistance model for the Poly-Si TFTs with LDD structure.