Modeling of the parasitic resistance effect in poly-Si TFTs with LDD structure

Abstract

In this study, the model of poly-Si TFTs with LDD structure had been proposed. Firstly, parasitic resistance parameters were extracted from devices with various channel length and LDD length. Then, an accurate I-V model was constructed by combining basic TFT model (RPI model) and the parasitic resistance effects. The model had been verified for devices with channel length larger than 6 mu m. The transconductance behavior in both linear region and saturation region are also well explained by our proposed model.