掃描式探針微影沉積金奈米粒子與硒化鎘量子點於電荷儲存之研究

Abstract

本研究將著重於兩個重點:其一是如何利用掃描式探針微影技術使奈米粒子選擇性沉積在所要的二氧矽表面區域;第二部分則是利用這些奈米粒子作成非揮發性記憶體電容結構並討論其電荷儲存的能力。 影響掃描試探針微影(SPL)技術在二氧化矽表面達成選擇性沉基金奈米粒子的製程參數在本實驗中被歸類:氧化層的厚度、探針掃描的速度以及探針所施加的偏壓。此外，利用SPL 技術所作的奈米圖案化製成，其解析度也達到100 奈米，可以媲美E-beam 微影技術。第二部分是將奈米粒子嵌入電容結構中作非揮發性奈米記憶體電容的相關探 討。本實驗使用兩種奈米粒子，即金奈米粒子(AuNPs)以及CdSe 量子點，探討其電荷儲存的能力。F-N 穿遂機制也將在本實驗中被介紹並驗證。此外本實驗所有的奈米粒子(金奈米粒子及硒化鎘量子點)在沉積時都於室溫下完成，避免了高溫製程(RTA)所造成的擴散現象而導致漏電的問題，改善了RTA 製程的缺失。令人關注的電荷儲存能力也將在C-V 圖等分析下探討。電荷保存能力也達到10e5 秒。配合記憶體元件多元化的閘極圖案，將來期望可利用SPL 技術將奈米粒子選擇性地沉積在想要的閘極區域，並利用這些奈米粒子作為非揮發性記憶體浮動閘極，以其改善傳統記憶體元件的特性。

This thesis is composed of two important parts. (1) The application of scanning probe lithography (SPL) to achieve selectively deposition of AuNPs on the silicon oxide (SiO2). (2)The electrical characteristics of the nonvolatile nanoparticle memory capacitors. (1) The effect of selectively deposition of AuNPs by SPL on the SiO2 might be due to the parameter of the thickness of SiO2, scanning speed and applied bias. Resolution of SPL nanopatterning is down to 100 nm, which is as well as E-beam lithography. (2) Capacitors with AuNPs, CdSe Qdots and mixed NPs ( AuNPs + CdSe Qdots) working in the F-N tunneling regime have been investigated. Nanoparticles of AuNPs and CdSe Qdots embedded in the structure of capacitor were fabricated under room temperature, which compared with the fabrication of RTA process, can improve the leakage problem of memory devices. Retention time is up to 105 sec has been achieved. All the charge storage characteristics for different devices were recorded by capacitance -voltage (C-V) measurements.