Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 蕭哲民 | en_US |
dc.contributor.author | 蔡淳仁 | en_US |
dc.date.accessioned | 2014-12-12T03:10:06Z | - |
dc.date.available | 2014-12-12T03:10:06Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009455585 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/82106 | - |
dc.description.abstract | 隨著各種多媒體視訊標準的發展,越來越多人努力設計可支援多視訊標準的系統單晶片。MPEG在2004年時成立了一個小組,希望可以設計出有彈性的多媒體視訊系統。本篇論文設計一系統單晶片架構可支援MPEG所提出的系統 | zh_TW |
dc.description.abstract | Due to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this thesis, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 多媒體 系統單晶片 | zh_TW |
dc.subject | SoC | en_US |
dc.title | 支援MPEG可重組視訊編碼運作模式之系統單晶片架構設計 | zh_TW |
dc.title | SoC architecture for MPEG Reconfigurable Video Coding Framework | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
Appears in Collections: | Thesis |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.