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dc.contributor.author蕭哲民en_US
dc.contributor.author蔡淳仁en_US
dc.date.accessioned2014-12-12T03:10:06Z-
dc.date.available2014-12-12T03:10:06Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009455585en_US
dc.identifier.urihttp://hdl.handle.net/11536/82106-
dc.description.abstract隨著各種多媒體視訊標準的發展,越來越多人努力設計可支援多視訊標準的系統單晶片。MPEG在2004年時成立了一個小組,希望可以設計出有彈性的多媒體視訊系統。本篇論文設計一系統單晶片架構可支援MPEG所提出的系統zh_TW
dc.description.abstractDue to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this thesis, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.en_US
dc.language.isoen_USen_US
dc.subject多媒體 系統單晶片zh_TW
dc.subjectSoCen_US
dc.title支援MPEG可重組視訊編碼運作模式之系統單晶片架構設計zh_TW
dc.titleSoC architecture for MPEG Reconfigurable Video Coding Frameworken_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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