标题: 应用于矽碟微控制器之平均磨损演算法的设计与实作
Design and implementation of an efficient wear-leveling algorithm for solid-state-disk micro controllers
作者: 杜俊达
Chun-Da Du
张立平
Li-Pin Chang
资讯学院资讯学程
关键字: 快闪记忆体;平均抹损;NAND;Flash;Wear Leveling
公开日期: 2006
摘要: 随着高容量的NAND 快闪记忆体可以越來越负担的起的时候,近來新兴的应用之一是矽碟机用來取代手持装置的硬碟。在实际上具有高度区域性工作量的矽碟机应用上,如果使用过去平均磨损演算法的适用性会被质疑。近年來研究人员提出了许多进阶的平均抹损演算法。然而,就我们所知,目前没有任何的进阶平均抹损演算法可以实作在只具有少數资源的矽碟微控器上。本篇論文试着拉近演算法与实作的差距。我们的挑战在于,如何使用有限的随机存取记忆体空间,去追踪记錄每一个快闪记忆体区块抹损的次數。基于之前所提出的方法,Dual-Pool演算法,我们只使用少于200 位元的随机存取记忆体,就可以有效的去平均抹损容量较大的NAND 快闪记忆体。
As high-capacity NAND flash is becoming affordable, one among the recently emerging applications is to replace hard drives in mobile computers with solid-state disks (SSDs). The applicability of naive wear-leveling algorithms is largely concerned by realistic SSD workloads because the access patterns comprise strong spatial localities. Researchers have recently proposed advanced wear-leveling algorithms. However, to our best knowledge, there is little work regarding how the advanced algorithms can be realized in resource-restrictive SSD controllers. This work tries to
close the gap between algorithms and implementation. The challenges pertain to how to use limited RAM space to keep track of the wearing of all the blocks. Based on a previously proposed, the dual-pool algorithm, we have shown that, by using no more than 200 bytes of RAM, wear leveling can be effectively conducted on a large NAND flash memory.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009467593
http://hdl.handle.net/11536/82495
显示于类别:Thesis


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