指令快取記憶體的電源管理-(對程式流程有感知能力的昏睡指令記憶體)

Abstract

指令快取記憶體的電源管理，其只要的概論是將處於工作模式的快取列的數量最小化。於是乎，在啟動的方案上，便是利用固定的目標位址使非循序的快取列預先活躍化。在關閉的方案上，在某一快取列最後一次使用並且將其內容物傳遞之後，此時便將此快取列關閉成昏睡模式。此概論的目的便是將漏電所產生的能耗減少到最少。在開啟的階段，由於快取記憶體的取代方案採用“關連性取代法”，如此導致會有好幾個的快取列同時活躍化。在一段覺醒時間之後，除了會參考到的快取列，將其餘不會參考的快取列切換成昏睡模式。這些額外增加的輔助硬體不只能提供下一個“基礎區塊”的預測能力，並且當“錯誤的預測”發生後能導正程式的流程。在實驗的結果顯示本論文建議的設計能減少的漏電能耗。當“覺醒潛在因素”是由一個clock的“覺醒時間”以及一個clock1本設計“電路延遲”。在一般的個例中，執行時間會增加10.898% 至 14.581% 已及減少77.5% 知82.4% 的漏電能耗。

Main concept of Power management of Instruction Cache - (Program Flow Sensitive Drowsy I-Cache (pfsDIC for brief)) is that minimize the numbers of active cache lines. So, on Turn-On scheme, utilize fixed Target address to preactivate the discontinuous Instruction Cache Line. On Turn-Off scheme, turn-off the cache lines after the last content of this cache line is transmitted. The purpose of such concept is to reduce maximum leakage energy. On Turn-On stage, there is several cache lines are activating due to low-way associated. After an amount of wakeup time, switch these awaken cache lines to “Drowsy mode” except to the referred cache line. The additional auxiliary hardware don’t only offer the predictive ability of next Basic Block, but also maintain the correct program flow when wrong prediction happens. The experiment results show the leakage reduction of proposed designs. When the wakeup latency is the sum of 1 clock of wakeup time and an extra 1 clock of circuit delay that caused by proposed design. In the average case, the Runtime increment is 10.898%~14.581% and the leakage reduction is 77.5% ~ 82.4%