鎳金屬誘發側向結晶－低溫複晶矽薄膜電晶體之漏電流與可靠度研究

Abstract

在現今的消費市場上，薄膜電晶體液晶顯示器可以說應用地非常廣泛，而在提升效能所製作低溫複晶矽(LTPS)薄膜電晶體的方法中，利用鎳金屬誘發非晶矽薄膜側向結晶法(NILC)，能在較低退火溫度與較短退火時間下，得到不但均勻而且品質佳的結晶顆粒，而廣受矚目。對於鎳金屬誘發複晶矽薄膜來說，在誘發結晶過程中所殘留的鎳金屬，會被晶界及缺陷所捕捉並產生深層能階，進而造成漏電流與元件效能衰退，因此發展有效的捉聚鎳方法來降低鎳金屬誘發複晶矽薄膜中的鎳金屬殘留，與降低複晶晶界處的懸鍵及缺陷，是提升高效能及高品質薄膜電晶體的重要課題。 本研究主要是提供一個簡易而有效的分析方法，透過不同製程手法改善電晶體效能的試片，來探討NILC-LTPS TFT漏電流產生的來源，及其改善的效果，並進一步觀察對元件可靠度的影響。 大致上將薄膜電晶體的漏電流路徑分為四個部份來探討。(1)閘極氧化層漏電流(Gate oxide leakage current)。來自於不良的閘極氧化層蝕刻所形成的缺陷；或較差的閘極氧化層成長品質。(2)閘極引發汲極漏電流(Gate induced drain leakage current)。來自於施加在閘極與汲極間的高電場，引發汲極的漏電流產生。(3)接面漏電流 (Junction leakage current)。來自接面熱電子的放射；或熱電子場效放射；或電子的穿隧效應。(4)通道漏電流(Channel leakage current)。來自通道因電場擊穿效應；汲極施加電壓引發晶格能障下降，而產生漏電流增加；金屬殘留所產生的漏電流路徑。可利用電性量測的分析手法，進一步了解各路徑的貢獻及主因為何。 薄膜電晶體在頻繁地操作下，因電場及溫度效應，會對元件產生程度不一的劣化，會導致電晶體的開啟電流(On current)下降、起始電壓(Threshold voltage)上升及漏電流(Leakage current)的增加，造成元件操作效能降低。於此，將元件可靠度部份，分為兩個方面來探討。一個是對元件施加偏壓及溫度效應的不穩定性(Bias Temperature Instabilty)，主要來自於閘極施加一電場時，在溫度效應下，閘極氧化層與複晶矽界面處的Si-H鍵會被打斷，並形成氫氣氣體，經由擴散效應而帶離閘極氧化層，進而在界面處產生懸鍵，使元件產生劣化的效應。另一個是熱載子效應(Hot Carriers effect Injection)，主要來自於電晶體在開啟狀態下，汲極所施加的電壓會產生一強大的電場，使得加速載子衝擊中性原子，而形成解離現象，產生電子與電洞對。此時被激化電子或電洞會再衝擊閘極氧化層，造成層面處的缺陷捕捉(Interface trap states)；或陷入層極氧化層中，使元件產生劣化的效應。 試片的準備分為兩個部份。第一個是NILC-LTPS TFT製造過程中，在NILC Poly-Si 的表面上，施加混合四氟化碳電漿(CF4 plasma)的蝕刻氣體，來進行表面處理。一方面透過輕微的轟擊蝕刻，可以減少表面的鎳金屬雜質的殘留，另一方面藉由氟與矽原子的鍵結，來鈍化晶界的懸鍵以減少晶界中的有效捕陷數目，進而改善元件效能。第二個是製造過程中，在元件汲極與源極的金屬配線接觸窗開啟時，鍍上一層非晶矽薄膜，來進行鎳金屬的捉聚，進而降低鎳金屬在電晶體通道中的含量，來提升元件效能。

TFT display panels are widely used for consumer products on worldwide market. Among various techniques of fabricating Low Temperature Polycrystalline Silicon(LTPS) thin film to obtain higher performance TFTs, Nickel metal-Induced Lateral Crystallization(NILC) attracted considerable interest for their better uniformity and crystal quality acquired at lower annealing temperature and shorter annealing time. However, in the processing of NILC Poly-Si, residual Ni trapped by the grain boundaries and defects leads to introduce deep level states and results in degradation of the device performance. Therefore, it’s very important to fabricate NILC-LTPS TFT with higher performance and quality by reducing Ni contaminations and dangling bonds of NILC Poly-Si thin film. This study mainly provide simple and effective procedures to figure out the leakage current paths of NILC-LTPS TFT by using performance improved TFT samples with various process splits. Then, the influence of device reliability would be also observed. The leakage paths of NILC-LTPS TFT are divided 4 parts to do discussion. (1)Gate oxide leakage current, which is from bad oxide etching profile, or bad oxide growth quality. (2)Gate induced drain leakage current, which is from higher electric filed applied between gate and drain to induce drain leakage current. (3)Junction leakage current, which is from thermionic emission, thermionic field emission, and pure tunneling of the PN junction. (4)Channel leakage current, which is from electric field punch through, drain indruced grain barrier lowing, and metal contaminations. Using electrical measurement methods to figure out which one is key factor. TFTs performance would be degraded under frequently operation with effects of electric filed and temperature, then induced on-current reducing, threshold voltage raising, and leakage current increasing. Herein, there are two parts to discuss device reliability. The first one is Bias Temperature Instability(BTI), which is a device degradation effect from dangling bonds of the interface between gate oxide and Poly-Si are generated by Si-H bonds broken under voltage bias gate and high temperature environment with combinated Hydrogen diffusing out. Another one is Hot Carriers effect Injection(HCI), which is degraded from interface trap states increased by gate oxide bombarding of impact ionization. The ionization electrons and holes are generated by impact from accelerating carriers to neutral atoms under high electric field of voltage bias drain on device on-state. Two experiement samples are demonstrated in this study. One is NILC Poly-Si with interface treatment of CF4 plamsa etching gas before gate oxide deposition. This method could improve device performance with reduction of Ni metal residues by slightly plasma bombarding and decrease of grain boundary trap states by bonding of Fluorine and Silicon. Another one is raising device performance with decrease of Ni contamination by amorphous Si gettering of source/drain side through metal contact via.