MIM電容結構下電極材料特性與漏電流關係之研究

Abstract

雙層MMC電容結構，是在電容面積維持不變，且不影響崩潰電壓條件下，得到雙倍電容結果的一個極佳的解決方案。實驗結果發現在電容金屬下電極使用較低溫度成長氮化鈦薄膜，會造成金屬下電極不同的表面粗糙度，且因不同的應力結果，導致以 SiO2 為介電層材料之針孔效應惡化。表面粗糙度變大及介電層針孔效應惡化皆會造成電容漏電流增加，崩潰電壓下降。而高溫濺鍍法沉積氮化鈦薄膜可得到較小的表面粗糙度，且因與後面高溫製程有較小的介面應力，故可減少介電材料的針孔效應，大幅改善崩潰電壓及電容漏電流結果。但對於以Si3N4或ONO堆疊為介電層材料的MIM電容，因其耐應力強度比SiO2高，故不同溫度下成長金屬下電極的氮化鈦薄膜對介電層針孔效應及電容漏電程度，則沒有明顯影響。

Double MMC (Metal Insulator Metal Capacitor) structure is one of the high capacitor solutions for saving chip size by stacking two dielectric layers of capacitor area without impacting Breakdown Voltage. We found that ARC TTN (Anti-Reflect Coating Ti/TiN) for SiO2 capacitor bottom plate metal with lower process temperature will lead to worse metal surface roughness and more compressive capacitor dielectric. The Stress difference will affect dielectric pinhole level. Both metal roughness and dielectric pinhole cause capacitor leakage current higher. But higher temperature TTN capacitor bottom plate metal with PVD process will not. So it can get better capacitor breakdown voltage. And double MMC with Si3N4, or ONO stack film dielectric have neither serious pinhole nor worse leakage current impact.