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dc.contributor.authorWu, I-Weien_US
dc.contributor.authorHuang, Shih-Chiaen_US
dc.contributor.authorChung, Chung-Pingen_US
dc.contributor.authorShann, Jyh-Jiunen_US
dc.date.accessioned2014-12-08T15:10:55Z-
dc.date.available2014-12-08T15:10:55Z-
dc.date.issued2007en_US
dc.identifier.isbn978-3-540-69337-6en_US
dc.identifier.issn0302-9743en_US
dc.identifier.urihttp://hdl.handle.net/11536/8346-
dc.description.abstractIn this paper, we propose new algorithms for both ISE exploration and selection with considering important physical constraints such as pipestage timing and instruction set architecture (ISA) format, silicon area and register file. To handle these considerations, an ISE exploration algorithm is proposed. It not only explores ISE candidates but also their implementation option to minimize the execution time meanwhile using less silicon area. In ISE selection, many researches only take silicon area into account, but it is not comprehensive. In this paper, we formulate ISE selection as a multiconstrained 0-1 knapsack problem so that it can consider multiple constraints. Results with MiBench indicate that under same number of ISE, our approach achieves 69.43%, 1.26% and 33.8% (max., min. and avg., respectively) of further reduction in silicon area and also has maximally 1.6% performance improvement compared with the previous one.en_US
dc.language.isoen_USen_US
dc.subjectinstruction set extensionen_US
dc.subjectASIPen_US
dc.subjectextensible processorsen_US
dc.subjectpipestage timing constrainten_US
dc.titleInstruction set extension generation with considering physical constraintsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalHigh Performance Embedded Architectures and Compilers, Proceedingsen_US
dc.citation.volume4367en_US
dc.citation.spage291en_US
dc.citation.epage305en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000244800700020-
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