Title: | Optimal design of triple-gate devices for high-performance and low-power applications |
Authors: | Chiang, Meng-Hsueh Lin, Jeng-Nan Kim, Keunwoo Chuang, Ching-Te 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Keywords: | corner effects;polysilicon gate;triple-gate (TG);MOSFETs |
Issue Date: | 1-Sep-2008 |
Abstract: | Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V(T)'s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented. |
URI: | http://dx.doi.org/10.1109/TED.2008.927664 http://hdl.handle.net/11536/8391 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2008.927664 |
Journal: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 55 |
Issue: | 9 |
Begin Page: | 2423 |
End Page: | 2428 |
Appears in Collections: | Articles |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.