標題: A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
作者: Lin, Yu-Kun
Lin, Chia-Chun
Kuo, Tzu-Yun
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Digital circuits;high-definition television (HDTV);H.264;motion estimation (ME);video coding;video signal processing
公開日期: 1-Jul-2008
摘要: Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 p @ 60 fps videos with +/- 128 search range within just 256 cycles, 5.95-KB buffers, and 213.7K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-mu m process can support processing of 1080 p @ 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design.
URI: http://dx.doi.org/10.1109/TCSI.2008.916681
http://hdl.handle.net/11536/8606
ISSN: 1549-8328
DOI: 10.1109/TCSI.2008.916681
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 55
Issue: 6
起始頁: 1526
結束頁: 1535
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