Analysis of P-type poly-Si TFT degradation under dynamic gate voltage stress using the slicing model

Abstract

In this work, the mobility degradation after gate AC stress in the off region are examined. It is discovered that the mobility increases after AC gate stress condition 0 V to + 15 V, which the previously reported model (by Uraoka. Y) may not explain. Considering the spatial distribution of the voltage and the flow of the carriers in the channel, we proposed the slicing model", that is, replace the original TFT by ten TFTs with shorter channel length. Then, by applying the circuit simulator, the voltage distribution in the channel under different stages of gate applied voltage may be obtained. An index considering the current flow and the channel voltage at the edge nodes are proposed to describe the degradation in mobility. The fair linearity between the proposed index and the degradation in mobility reveals the validity of the proposed model.