系統晶片設計平面規劃之研究

Full metadata record

DC Field	Value	Language
dc.contributor.author	張耀文	en_US
dc.contributor.author	YAO-WENCHANG	en_US
dc.date.accessioned	2014-12-13T10:29:26Z	-
dc.date.available	2014-12-13T10:29:26Z	-
dc.date.issued	2000	en_US
dc.identifier.govdoc	NSC89-2215-E009-117	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/89288	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=583930&docId=109717	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	系統晶片設計平面規劃之研究	zh_TW
dc.title	Floorplans for Systems-on-a-Chip Design	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學資訊科學學系	zh_TW
Appears in Collections:	Research Plans

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