Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

Abstract

To extend a carrier mobility improvement by strain engineering in high-density and small-gate-space complementary metal-oxide-semiconductor (CMOS) circuits, we have proposed a new stress memorization technique (SMT) that uses a strain proximity free technique (SPFT) to demonstrate the mobility improvement through multiple strain-gate engineering. The electron mobility of n-channel metal-oxide-semiconductor (MOS) field-effect transistors with the SPFT exhibits a 14% increase over counterpart techniques. Compared with the conventional SMT, the SPFT avoids the limitation of the stressor volume for the performance improvement in high-density CMOS circuits. We also found that the preamorphous layer (PAL) gate structure in combination with the SPFT can improve the mobility further to 31% greater than standard devices. Moreover, an additional 30% mobility enhancement can be achieved by using a dynamic threshold-voltage MOS and combining the PAL gate structure with the SPFT, respectively. The gate-oxide reliability and the channel-hot-carrier reliability are also analyzed. Our results show a mobility improvement by the SPFT, a slightly increased gate leakage current, and degraded channel-hot-carrier reliability.