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dc.contributor.authorChen, W. B.en_US
dc.contributor.authorShie, B. S.en_US
dc.contributor.authorChin, Alberten_US
dc.date.accessioned2014-12-08T15:11:49Z-
dc.date.available2014-12-08T15:11:49Z-
dc.date.issued2011-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2011.2106478en_US
dc.identifier.urihttp://hdl.handle.net/11536/9072-
dc.description.abstractBy applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO(2)/La(2)O(3)/SiO(2) on Ge n-MOSFETs shows a high gate capacitance density, a small n(+)/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm(2)/V . s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO(2)/Si universal mobility.en_US
dc.language.isoen_USen_US
dc.subjectAnnealingen_US
dc.subjectgate dielectricen_US
dc.subjectGeen_US
dc.subjecthigh-kappaen_US
dc.subjectlaseren_US
dc.titleHigher Gate Capacitance Ge n-MOSFETs Using Laser Annealingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2011.2106478en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume32en_US
dc.citation.issue4en_US
dc.citation.spage449en_US
dc.citation.epage451en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000288664800007-
dc.citation.woscount9-
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