系統封裝基板之關鍵技術研究

Abstract

本計劃將研究系統封裝基板的關鍵技術。包含: (1)基板設計與製造整合;(2)電性 模擬，量測與可靠度提升。在系統封裝基板方面，我們對內藏式被動元件系統做先期 的電路設計與電路模擬。電路的模擬可以針對電阻的電阻率以及電阻和電容的幾何結 構做考量與設計。當內藏式被動元件系統整合了低介電材料系統之後，我們可以就系 統封裝基板做電性量測，驗證，分析以及可靠度的分析與提升。經由本計畫的執行， 我們將會探討系統封裝內被動元件系統的I-V，C-V 的電性分析與可靠度分析，以及進 一步的提升系統封裝基板的效能。計劃內容包括： 1. 內藏式電阻與內藏式電容之製作與製程步驟相容性分析。 2. 低介電材料之評估與製備。 3. 系統封裝內的被動元件整合。 4. 建構一系統封裝基板。 5. 系統封裝基板的電性量測，分析與探討。

This study focuses on the key technologies of the integral substrate for system in package(SIP), including: (1)the fabrication and integration of substrate for system in package and (2)simulation, measurement and reliability study of the integral substrates. The material properties and the geometry of embedded resistors/capacitors are the parameters for simulation and design. The current-voltage, capacitance-voltage characteristics as well as the reliability of the embedded components are studied. This project includes: 1. Fabrication and process compatibility study of embedded resistor and embedded capacitor. 2. The evaluation and fabrication of low dielectric constant materials as inter-metallic dielectrics. 3. The integration of embedded components for system in package. 4. The fabrication of integral substrate for system in package. 5.Evaluation and analysis of the integral substrate for system in package.