| 標題: | 針對晶片系統連接網路之驗證與自動合成之研究(II) The Study on Interconnection Verification and Synthesis for SoC (II) |
| 作者: | 周景揚 JOU JING-YANG 國立交通大學電子工程學系 |
| 公開日期: | 2003 |
| 官方說明文件#: | NSC92-2215-E009-033 |
| URI: | http://hdl.handle.net/11536/91769 https://www.grb.gov.tw/search/planDetail?id=873468&docId=167334 |
| Appears in Collections: | Research Plans |
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- 針對晶片系統連接網路之驗證與自動合成之研究(I) / 周景揚;JOU JING-YANG
- 針對晶片系統連接網路之驗證與自動合成之研究(III) / 周景揚;JOU JING-YANG
- An automorphic approach to verification pattern generation for SoC design verification using port-order fault model / Wang, CY;Tung, SW;Jou, JY
- Automatic interconnection rectification for SoC design verification based on the port order fault model / Wang, CY;Tung, SW;Jou, JY
- On automatic-verification pattern generation for SoC with port-order fault model / Wang, CY;Tung, SW;Jou, JY
- 多媒體系統晶片設計技術之究---子計畫V：系統晶片上系統驗證之研究(II) / 周景揚;JOU JING-YANG
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