極低介電常數材料(k<2.2)與銅製程在超大型積體電路上之應用研究(II)

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DC Field	Value	Language
dc.contributor.author	施敏	en_US
dc.contributor.author	SZE SIMON MIN	en_US
dc.date.accessioned	2014-12-13T10:33:57Z	-
dc.date.available	2014-12-13T10:33:57Z	-
dc.date.issued	2003	en_US
dc.identifier.govdoc	NSC92-2215-E009-020	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/92397	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=873432&docId=167324	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	極低介電常數材料(k<2.2)與銅製程在超大型積體電路上之應用研究(II)	zh_TW
dc.title	Study on the Integration of Ultra Low k(k<2.2) and Copper Interconnect in ULSI Application (II)	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
Appears in Collections:	Research Plans

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