Capacitance-voltage behaviors of the LTPS TFTs before and after DC stress explained by the slicing model

Abstract

The proposed analytical circuit based on the slicing model further explains the behavior of the gate-to-source capacitance CGS and gate-to-drain capacitance CGD curves of the LTPS TFT at different measuring frequencies. The degradation mechanisms and damaged locations can be identified according to the frequency responses of the CGS and CGD curves.