標題: Capacitance-voltage behaviors of the LTPS TFTs before and after DC stress explained by the slicing model
作者: Kuo, Yan-Fu
Huang, Shih-Che
Chao, Yu-Te
Tai, Ya-Hsiang
光電工程學系
Department of Photonics
關鍵字: poly-Si TFTs;capacitance-voltage;slicing model;DC stress degradation
公開日期: 2007
摘要: The proposed analytical circuit based on the slicing model further explains the behavior of the gate-to-source capacitance CGS and gate-to-drain capacitance CGD curves of the LTPS TFT at different measuring frequencies. The degradation mechanisms and damaged locations can be identified according to the frequency responses of the CGS and CGD curves.
URI: http://hdl.handle.net/11536/9268
ISBN: 978-957-28522-4-8
期刊: IDMC'07: PROCEEDINGS OF THE INTERNATIONAL DISPLAY MANUFACTURING CONFERENCE 2007
起始頁: 523
結束頁: 525
Appears in Collections:Conferences Paper