Title: 高性能混合訊號式發收機積體電路---子計畫III:高速雙絞線網路發收機單晶片系統(III)
High-Speed Twisted-Pair Network Transceiver System on A Chip(III)
Authors: 吳介琮
WU JIEH-TSORNG
交通大學電子工程系
Keywords: 收發器;系統晶片;高速網路;Transceiver;System-on-chip (SOC);High speed network
Issue Date: 2001
Gov't Doc #: NSC90-2215-E009-110
URI: http://hdl.handle.net/11536/93455
https://www.grb.gov.tw/search/planDetail?id=665821&docId=126404
Appears in Collections:Research Plans


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