超大型積體電路之測試與可測試設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	李崇仁	en_US
dc.date.accessioned	2014-12-13T10:36:52Z	-
dc.date.available	2014-12-13T10:36:52Z	-
dc.date.issued	1999	en_US
dc.identifier.govdoc	NSC88-2215-E009-062	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/94228	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=418219&docId=74193	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	超大型積體電路	zh_TW
dc.subject	可測試性設計	zh_TW
dc.subject	靜態電流測試	zh_TW
dc.subject	振盪環測試	zh_TW
dc.subject	錯誤診斷	zh_TW
dc.subject	VLSI	en_US
dc.subject	IDDQ testing	en_US
dc.subject	Burn-in testing	en_US
dc.subject	Oscillation ring testing	en_US
dc.subject	Fault diagnosis	en_US
dc.title	超大型積體電路之測試與可測試設計	zh_TW
dc.title	VLSI Testing and Design for Testability	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
Appears in Collections:	Research Plans

Files in This Item:

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.