單晶片多處理機設計之研究---子計畫III：單晶片多處理機可程式實驗平台之設計與實現(III)

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DC Field	Value	Language
dc.contributor.author	王國禎	en_US
dc.contributor.author	WANG KUO-CHEN	en_US
dc.date.accessioned	2014-12-13T10:37:21Z	-
dc.date.available	2014-12-13T10:37:21Z	-
dc.date.issued	1999	en_US
dc.identifier.govdoc	NSC88-2213-E009-039	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/94570	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=442129&docId=79964	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	多處理器	zh_TW
dc.subject	單邊縱橫交換鍵	zh_TW
dc.subject	疊流式交換鍵控制協定	zh_TW
dc.subject	互接網路	zh_TW
dc.subject	硬體描述語言	zh_TW
dc.subject	現場可程式閘陣列	zh_TW
dc.subject	Multiprocessor	en_US
dc.subject	One sided crossbar switch	en_US
dc.subject	Pipelined switch control protocol	en_US
dc.subject	Interconnection network	en_US
dc.subject	Hardware description language (HDL)	en_US
dc.subject	Field programmable gate array (FPGA)	en_US
dc.title	單晶片多處理機設計之研究---子計畫III：單晶片多處理機可程式實驗平台之設計與實現(III)	zh_TW
dc.title	Design and Implementation of a Programmable Experimental Platform for a Single Chip with Multiple CPUs (III)	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學資訊科學研究所	zh_TW
Appears in Collections:	Research Plans

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