Title: 單晶片多處理機設計之研究---子計畫三:單晶片多處理機可程式實驗平台之設計與實現(II)
Design and Implementation of a Programmable Experimental Platform for a Single Chip with Multiple CPUs (II)
Authors: 王國禎
WANG KUO-CHEN
交通大學資訊科學系
Keywords: 單邊縱橫交換鍵;容錯;疊流式交換鍵控制協定;標準硬體描述語言;現場可程式邏輯陣列;對稱式多處理機;現場可程式電路板;One-sided crossbar switch;Fault tolerance;Pipelined switch control protocol;Verilog;Field programmable gate array;Symmetric multiprocessor;Field programmable circuit board
Issue Date: 1998
Gov't Doc #: NSC87-2213-E009-030
URI: http://hdl.handle.net/11536/94971
https://www.grb.gov.tw/search/planDetail?id=375268&docId=67564
Appears in Collections:Research Plans


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