完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Kuo, Chien-I | en_US |
dc.contributor.author | Hsu, Heng-Tung | en_US |
dc.contributor.author | Chang, Edward Yi | en_US |
dc.contributor.author | Chang, Chia-Yuan | en_US |
dc.contributor.author | Miyamoto, Yasuyuki | en_US |
dc.contributor.author | Datta, Suman | en_US |
dc.contributor.author | Radosavljevic, Marko | en_US |
dc.contributor.author | Huang, Guo-Wei | en_US |
dc.contributor.author | Lee, Ching-Ting | en_US |
dc.date.accessioned | 2014-12-08T15:12:22Z | - |
dc.date.available | 2014-12-08T15:12:22Z | - |
dc.date.issued | 2008-04-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2008.917933 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/9505 | - |
dc.description.abstract | Eighty-nanometer-gate In0.7Ga0.3As/InAs/ In0.7Ga0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250 degrees C for 3 min, the device exhibited a high g(m) value of 1590 mS/mm at V-d = 0.5 V, the current-gain cutoff frequency f(T) was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f(T) achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | High-electron mobility transistors (HEMTs) | en_US |
dc.subject | InAs | en_US |
dc.subject | InGaAs | en_US |
dc.subject | platinum (Pt) buried gate | en_US |
dc.title | RF and logic performance improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite-channel HEMT using gate-sinking technology | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2008.917933 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 29 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.spage | 290 | en_US |
dc.citation.epage | 293 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000254225800003 | - |
dc.citation.woscount | 13 | - |
顯示於類別: | 期刊論文 |