針對用戶可規劃閘陣列的面積與速度最佳化暨分割之研究

Full metadata record

DC Field	Value	Language
dc.contributor.author	沈文仁	en_US
dc.date.accessioned	2014-12-13T10:38:07Z	-
dc.date.available	2014-12-13T10:38:07Z	-
dc.date.issued	1998	en_US
dc.identifier.govdoc	NSC87-2215-E009-040	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/95086	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=409078&docId=72427	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	場可程式閘列	zh_TW
dc.subject	合成	zh_TW
dc.subject	分割	zh_TW
dc.subject	電路叢集	zh_TW
dc.subject	面積	zh_TW
dc.subject	功能	zh_TW
dc.subject	Field programmable gate array	en_US
dc.subject	Synthesis	en_US
dc.subject	Partitioning	en_US
dc.subject	Circuit clustering	en_US
dc.subject	Area	en_US
dc.subject	Performance	en_US
dc.subject	FPGA	en_US
dc.title	針對用戶可規劃閘陣列的面積與速度最佳化暨分割之研究	zh_TW
dc.title	A Study of Area/Performance Optimization and Partitioning for Field Programmable Gate Arrays	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
Appears in Collections:	Research Plans