Title: 針對用戶可規劃閘陣列的面積與速度最佳化暨分割之研究
A Study of Area/Performance Optimization and Partitioning for Field Programmable Gate Arrays
Authors: 沈文仁
交通大學電子工程系
Keywords: 場可程式閘列;合成;分割;電路叢集;面積;功能;Field programmable gate array;Synthesis;Partitioning;Circuit clustering;Area;Performance;FPGA
Issue Date: 1998
Gov't Doc #: NSC87-2215-E009-040
URI: http://hdl.handle.net/11536/95086
https://www.grb.gov.tw/search/planDetail?id=409078&docId=72427
Appears in Collections:Research Plans