積體電路生產線上利用類神經網路方法分析缺陷群聚現象之修正缺陷數管制圖

Title:	積體電路生產線上利用類神經網路方法分析缺陷群聚現象之修正缺陷數管制圖 Modified Process Control Chart in Integrated Circuits Fabrication---Using Neural Network
Authors:	唐麗英 TONG LEE-ING 交通大學工業工程與管理系
Keywords:	積體電路;良率;缺陷;波瓦松分配;缺陷數管制圖;類神經網路;群聚;Integrated circuit;Yield;Defect;Poisson distribution;C-Chart;Neural network;Clustering
Issue Date:	1997
Gov't Doc #:	NSC86-2213-E009-035
URI:	http://hdl.handle.net/11536/95390 https://www.grb.gov.tw/search/planDetail?id=269137&docId=47931
Appears in Collections:	Research Plans