良率分析應用於動態隨機存取記憶體中區域分割及修復電路之研究

Full metadata record

DC Field	Value	Language
dc.contributor.author	唐麗英	en_US
dc.contributor.author	TONG LEE-ING	en_US
dc.date.accessioned	2014-12-13T10:39:03Z	-
dc.date.available	2014-12-13T10:39:03Z	-
dc.date.issued	1996	en_US
dc.identifier.govdoc	NSC85-2213-E009-129	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/96015	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=218522&docId=38688	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	良率分析應用於動態隨機存取記憶體中區域分割及修復電路之研究	zh_TW
dc.title	Yield Analysis with Division of Sections and Redundancy Scheme for DRAM	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學工業工程與管理學系	zh_TW
Appears in Collections:	Research Plans