資料路徑合成多重輸出入埠記憶體分配埠使用率研究

Full metadata record

DC Field	Value	Language
dc.contributor.author	蕭培墉	en_US
dc.contributor.author	HSIAO PEI-YUNG	en_US
dc.date.accessioned	2014-12-13T10:39:42Z	-
dc.date.available	2014-12-13T10:39:42Z	-
dc.date.issued	1995	en_US
dc.identifier.govdoc	NSC84-2213-E009-017	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/96762	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=160927&docId=26765	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	資料路徑合成多重輸出入埠記憶體分配埠使用率研究	zh_TW
dc.title	Research on Ports Utilization for Multiport Memories in Allocation in Data Path Synthesis	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學資訊科學研究所	zh_TW
Appears in Collections:	Research Plans