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dc.contributor.authorChen, Shih-Hungen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:12:36Z-
dc.date.available2014-12-08T15:12:36Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1014-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/9679-
dc.description.abstractPMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, turned-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.en_US
dc.language.isoen_USen_US
dc.titleOptimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-mu m CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITSen_US
dc.citation.spage245en_US
dc.citation.epage248en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000251130700046-
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