On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation

Abstract

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-mu m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.