電子可擦式記憶元件及電路之可靠度研究與改進

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	吳重雨	en_US
dc.date.accessioned	2014-12-13T10:40:59Z	-
dc.date.available	2014-12-13T10:40:59Z	-
dc.date.issued	1993	en_US
dc.identifier.uri	http://hdl.handle.net/11536/98065	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=6007&docId=563	en_US
dc.description.abstract	ぇ於HMC現有的Process架構下,改變Process參數:用既有的結構(如EEPROM, DRAM, etc..),改變SiO/sub 2/之厚度(如Tunnel Oxide或InterpolyOxide),以觀察在各情況下 F-N Tunneling和Hot-carrier相互消長的情形.亦可改變 Interpoly Oxide之材質(如將SiO/sub 2/改為Si/sub 3/N/sub4 /),以測量其Retention及Coupling Ratio之變化,並就以上測量結果提出最佳狀況之條件.え寄放於HMC將出的New Product之Test Key內,設計New Structures:a, CMOS Process Compatible EEPROM.b, 用DRAM之PROCESS,設計New Structure, Combines both DRAM and EEPROMCells.c,MONOS.d,Flash EEPROM, by EEPROM Process.ぉ就HMC所提供量產的元件作特性量測:a,High-frequency Program/Erase.可使EERPOM具有Selective Programming/Erasing,較低的 Electric FieldAcross Oxide, Endurance更好.Self Limited:不會Over Erase.b,Low-Temperature Characterization.在低溫超導的趨式Memory-Device應用在Low Temperature 勢必為未來趨式,而且是一個新的領域.c,Degradation的研究:	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	華隆微電子	zh_TW
dc.subject	氮化矽	zh_TW
dc.subject	電子可擦式記憶元件	zh_TW
dc.subject	動態隨機存取記憶體	zh_TW
dc.subject	製程	zh_TW
dc.subject	互補式金氧半電晶體	zh_TW
dc.subject	二氧化矽	zh_TW
dc.subject	頹敗	zh_TW
dc.subject	HMC	en_US
dc.subject	Si3N4	en_US
dc.subject	EEPROM	en_US
dc.subject	DRAM	en_US
dc.subject	Process	en_US
dc.subject	CMOS	en_US
dc.subject	SiO2	en_US
dc.subject	Degradation	en_US
dc.title	電子可擦式記憶元件及電路之可靠度研究與改進	zh_TW
dc.title	Research and Improvement of EEPROM Device and Reliability	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程研究所(NCTEELN)	zh_TW
顯示於類別：	研究計畫