Miniature RF test structure for on-wafer device testing and in-line process monitoring

doi:10.1109/TED.2007.911037

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Cho, Ming-Hsiang	en_US
dc.contributor.author	Lee, Ryan	en_US
dc.contributor.author	Peng, An-Sam	en_US
dc.contributor.author	Chen, David	en_US
dc.contributor.author	Yeh, Chune-Sin	en_US
dc.contributor.author	Wu, Lin-Kun	en_US
dc.date.accessioned	2014-12-08T15:12:44Z	-
dc.date.available	2014-12-08T15:12:44Z	-
dc.date.issued	2008-01-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TED.2007.911037	en_US
dc.identifier.uri	http://hdl.handle.net/11536/9807	-
dc.description.abstract	In this brief, a miniature test structure for RF device characterization and process monitoring has been proposed. This new layout design can minimize the voltage drop across interconnects and can prevent capacitive coupling to devices. It consumes only 36% and 40% of the chip area of the conventional on-wafer and in-line test structures, respectively. The RF characteristics of the proposed test structure are shown to be in excellent agreement with those of the conventional ones.	en_US
dc.language.iso	en_US	en_US
dc.subject	MOSFET	en_US
dc.subject	process monitoring	en_US
dc.subject	RF	en_US
dc.subject	scribe line	en_US
dc.subject	test structure	en_US
dc.title	Miniature RF test structure for on-wafer device testing and in-line process monitoring	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TED.2007.911037	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	55	en_US
dc.citation.issue	1	en_US
dc.citation.spage	462	en_US
dc.citation.epage	465	en_US
dc.contributor.department	電信工程研究所	zh_TW
dc.contributor.department	Institute of Communications Engineering	en_US
dc.identifier.wosnumber	WOS:000252059000050	-
dc.citation.woscount	2	-
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