前瞻性混合信號式電路設計技術開發-子計畫一：低耗能光連結系統收發機積體電路(I)

Abstract

本計畫之目標為研發低耗能之多通道光收發機積體電路，以應用在短距離之高速連結系統。在傳送端，將透過低電流驅動之 VCSEL 雷射二極體進行信號調變，同時研發主動式負載匹配網路，以達到低耗能之目的。雷射輸出光信號將藉由多模式光纖(multi-mode fiber) 或光波導進行信號傳播到接收端。在接收電路方面，將採取積分取樣之方式，同時結合時脈延遲鎖定及時脈與資料回復電路，相較於傳統類比式的轉阻及限幅放大器接收機，其預期可大幅降低功率消耗。此外，並將研發可整合於單一晶片內的 CMOS 光感測器，利用新型感測器以克服傳統矽光感測器靈敏度與頻寬不足之問題。 本計劃整合 CMOS 光感測器之低耗能光連結系統，重點內容包含等化器技術、多通道資料還原電路、高頻阻抗匹配與位準校正技術，及高速 (100 Gb/s) 內建式自我測式系統與傳輸錯誤率估計技術。同時，本計劃將著力於電路技術之發展，以期實現高速、低錯誤率、與低功率消耗之目標。藉此達到高整合度、低成本、低耗能且整體的資料速度達到 100 Gb/s 以上之目標 本計畫中傳輸接收端之各子電路模組將經由仔細之設計、模擬、佈局、檢測、與驗證。電路之製造將委由國科會晶片設計製造中心 (CIC) 以及台灣積體電路製造股份有限公司 (TSMC) 下線。預料本計畫之研究成果對於國內傳輸介面電路技術之發展，將可提供直接之助益。

The objective goal of this project is to develop low-power and multi-channels transceiver ICs for short-reach optical interconnects. At the transmitter side, a low- modulation-current VCSEL driver incorporating an active back-termination (ABT) network transmits the data through multi-mode fibers (MMF) or on-chip waveguides to achieve low-power requirement. An integrating and dump optical receiver incorporating delay-locked loop and clock and data recovery circuit will be adopted to replace conventional trans-impedance amplifier and a post-limiting amplifier, which is expected to drastically reduce power consumption. Additionally, a novel CMOS photo-detector (PD) integrated with signal conditioning circuitries will be developed to detect the 850-nm light source and boost their responsivity and bandwidth. The major working tasks include high-sensitivity O/E converters with CMOS photo detectors, digital intensive receiver architecture, high-speed mixed-mode equalizer, multi-channel clock and data recovery circuit, impedance matching network, 100-Gb/s build-in self test (BIST) and bit-error-rate (BER) measurement circuits. Furthermore, novel circuit techniques will be explored to achieve the ultimate goal of a high-speed, low BER, and low-power consumption 100-Gb/s optical transceiver system. All the sub-circuits of the high speed transceiver will be carefully designed, simulated, laid-out, verified, and measured. Fabrication will be coordinated by Chip Implementation Center (CIC) and Taiwan Semiconductor Manufacturing Company (TSMC). Circuit techniques come out with this project would be beneficial to the developing of high speed interface circuits for domestic industry.