互補式場效電晶體元件的高介電質材料電性

Abstract

高介電材料已經運用在 45 奈米的互補式場效電晶體、動態隨機存取記憶體與 非揮發性記憶體。根據Intel 的共同創造者，高登摩爾的說法「從1960 年後期， 高介電材料與金屬閘極材料對傳統使用結晶矽的閘極電晶體有了重大改變」。因 此，根據高登摩爾的理論，運用此技術將有可能獲得諾貝爾獎。在之前，我們是使 用高介電材料Al2O3 (發表於Intel. MBE Conference 1998；Symp. On VLSI 1999)與 La2O3 (發表於Symp. On VLSI 2000) 當閘極介電材料的先驅。而這兩種高介電材 料Al2O3 與La2O3 已經被IBM，AMD，Toshiba，Renseas，IMEC，SEMATECH 等 公司並且與HfSiO 整合在Gate-first 製程中，且成功的在32 奈米技術中做出低的「臨 界電壓」之n 與p 型互補式場效電晶體。然而，雖然J. Robertson 已經成功的提出 電荷轉移模型，不過一些詳細的機制我們還是不了解。儘管我們的研究已經成功提 出介面反應所產生的氧空隙缺陷模型，而且東京大學A. Toriumi 已提出的電荷耦極 的模型，但是其中的費米能階的札釘效應導致的不理想的高臨界電壓，這也是仍然 需要進一步研究的。不幸地，基本的理論將會是微縮等效氧化層厚度(EOT)關鍵。 此困難度可以從Intel 45 奈米結點1 奈米的EOT 到32 奈米結點只緩慢的微縮到0.9 奈米。而為了解決此問題，這也是台灣荊鳳德教授實驗室與俄羅斯西伯利亞分學院 半導體物理研究所的Gritsenko Vladimir Alexeevich 博士與他的團隊提出此計畫的 目的，俄羅斯團隊有很強的物理背景知識，而台灣荊教授實驗室則是對於元件有很 強的製作能力，這將是此合作的優勢。我們也將根據物理知識，目標製作出新的元 件並解決EOT 無法繼續微縮的問題。因此，也是台俄雙方運用科學與科技整合的 優勢。

High-κ dielectrics have been used for 45 nm node CMOSFETs, DRAM capacitor and non-volatile memory. According to Intel co-founder Gordon Moore, “The implementation of high-κ and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.” Therefore, it is possible to award a Nobel Laureates, according to Gordon Moore again. Previously, we pioneered the high-κ Al2O3 (Intl. MBE Conference 1998; Symp. on VLSI 1999) and La2O3 (Symp. on VLSI 2000) gate dielectrics as early as 1998. These high-κ Al2O3 and La2O3 gate dielectrics have been used with HfSiO for gate-first low threshold voltage (Vt) 32-nm node p- and n-MOSFETs respectively, by IBM, AMD, Toshiba, Renesas, IMEC, SEMATECH etc. The low threshold voltage Vt is due to the unique negative and positive charges in Al2O3 and La2O3 gate dielectrics respectively, which is most the only solution for needed high function p-MOSFET. However, the detailed mechanism is still uncertain, even though J. Robertson has proposed the charge transfer model. Besides, the Fermi-level pinning related unwanted high Vt in HfO2-based high-κ dielectric is still unclear, where both interface reaction formed oxygen vacancy model by us and charge dipole model by A. Toriumi at University of Tokyo were proposed. Unfortunately, the fundamental understanding is the key to further scaling down the equivalent-oxide thickness (EOT). Such difficult challenge can be evident from the slow down scaling the EOT: 1.0 nm for Intel’s 45-nm node CMOS to only slightly scaled 0.9 nm for 32-nm node technology. The purpose of this joint research project between Prof. Albert Chin’s group at Taiwan and Dr. Gritsenko Vladimir Alexeevich’s team at Institute of Semiconductor Physics, Siberian Branch of Russian Academy of Sciences is to understanding the fundamental physics for unique charge nature in high-κ Al2O3 and La2O3 gate dielectrics. Here the physics background is the strong merit of Russia team and the high-κ device fabrication is well developed in Prof. Chin’s group at Taiwan. Based on understating the physics, our goal is to propose novel device and process solution for highly scaled EOT metal-gate/high-κ CMOSFETs. Therefore, this should be benefit for both side of Taiwan and Russia that is a perfect match between science and technology.