學研合作計畫-次22奈米金屬閘極/高介電質場效電晶體及記憶體技術平台( I )

Abstract

我們已經製作出在磊晶Ge/Si基板上之高介電係數TaN/TiLaO/SiO2的n型金氧半場效電晶體(n-MOSFET)，並且研究具有不同GeO2和SiO2界面層的關係。具有超薄GeO2的電晶體界面顯示了較差的特性，較大1.1奈米的「等效氧化層厚度」，和不良的電容-電壓遲滯(93 mV)。從橫截面「透射電子顯微鏡」，「二次離子質譜儀」和「X射線光電子能譜」的分析，使用超薄GeO2界面層的元件性能退化，乃由於550℃快速熱退火後，Ge嚴重的向外擴散，界面GeO2的退化，以及閘極介電層增厚。Ge使用超薄SiO2界面層的n型場效電晶體具有3.3 F/cm2極大的電容密度，極小0.81奈米的「等效氧化層厚度」，大幅改善的電容-電壓遲滯(19 mV)，在有良好的遷移率201 cm2/Vs於0.5 MV/cm電場，以及非常低的關閉漏電流3.5×10-10 A/m。此Ge場效電晶體乃是使用及傳統閘極優先的製程、自我對準的離子佈植、550℃快速熱退火處理的方法，和當前的超大規模積體電路(VLSI)製造方法完全相容。

We have investigated the high-κ TaN/TiLaO n-MOSFETs on epitaxial-Ge/Si substrate, with different ultra-thin GeO2 and SiO2 interfacial layers. The high-κ TaN/TiLaO/GeO2 epitaxial-Ge/Si MOS capacitor shows a larger 1.1 nm equivalent- oxide-thickness (EOT) and poor C-V hysteresis of 93 mV. From the cross-sectional Transmission Electron Microscopy (TEM), Secondary Ion Mass Spectroscopy (SIMS) and X-ray Photoelectron Spectroscopy (XPS) analysis, the degraded device performance using ultra-thin GeO2 interfacial layer is due to the severe Ge out-diffusion, degraded GeO2 dielectric quality and thicker gate dielectric after 550oC RTA. In sharp contrast, the high-κ TaN/TiLaO/SiO2 epitaxial-Ge/Si n-MOSFETs with ultra-thin SiO2 interfacial layer showed a very large gate-capacitance density of 3.3F/cm2, a record small 0.81 nm EOT, a much-improved C-V hysteresis of only 19 mV, good medium-field mobility of 201 cm2/V-s at 0.5 MV/cm, and a very low off-state leakage current of 3.5×10-10 A/m. The metal-gate/high-κ/epitaxial-Ge/Si n-MOSFETs were fabricated using conventional self-aligned and gate-first process, with standard ion-implantation and 550oC RTA. The proposed devices are fully compatible with current VLSI fabrication methods.