完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Wu, Woei-Cherng | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.contributor.author | Peng, Wu-Chin | en_US |
dc.contributor.author | Yang, Wen-Luh | en_US |
dc.contributor.author | Chen, Jian-Hao | en_US |
dc.contributor.author | Ma, Ming Wen | en_US |
dc.contributor.author | Lai, Chao-Sung | en_US |
dc.contributor.author | Yang, Tsung-Yu | en_US |
dc.contributor.author | Lee, Chien-Hsing | en_US |
dc.contributor.author | Hsieh, Tsung-Min | en_US |
dc.contributor.author | Liou, Jhyy Cheng | en_US |
dc.contributor.author | Chen, Tzu Ping | en_US |
dc.contributor.author | Chen, Chien Hung | en_US |
dc.contributor.author | Lin, Chih Hung | en_US |
dc.contributor.author | Chen, Hwi Huang | en_US |
dc.contributor.author | Ko, Joe | en_US |
dc.date.accessioned | 2014-12-08T15:12:55Z | - |
dc.date.available | 2014-12-08T15:12:55Z | - |
dc.date.issued | 2008-01-01 | en_US |
dc.identifier.issn | 0268-1242 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1088/0268-1242/23/1/015004 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/9974 | - |
dc.description.abstract | In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V(TH) distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1088/0268-1242/23/1/015004 | en_US |
dc.identifier.journal | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | en_US |
dc.citation.volume | 23 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.epage | en_US | |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.identifier.wosnumber | WOS:000253279700004 | - |
dc.citation.woscount | 4 | - |
顯示於類別: | 期刊論文 |