標題: | Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory |
作者: | Wu, Woei-Cherng Chao, Tien-Sheng Peng, Wu-Chin Yang, Wen-Luh Chen, Jian-Hao Ma, Ming Wen Lai, Chao-Sung Yang, Tsung-Yu Lee, Chien-Hsing Hsieh, Tsung-Min Liou, Jhyy Cheng Chen, Tzu Ping Chen, Chien Hung Lin, Chih Hung Chen, Hwi Huang Ko, Joe 電子物理學系 Department of Electrophysics |
公開日期: | 1-一月-2008 |
摘要: | In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V(TH) distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance. |
URI: | http://dx.doi.org/10.1088/0268-1242/23/1/015004 http://hdl.handle.net/11536/9974 |
ISSN: | 0268-1242 |
DOI: | 10.1088/0268-1242/23/1/015004 |
期刊: | SEMICONDUCTOR SCIENCE AND TECHNOLOGY |
Volume: | 23 |
Issue: | 1 |
結束頁: | |
顯示於類別: | Articles |
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