極低蕭基位障與接觸電阻技術之研究(I)

Abstract

隨金氧半場效電晶體的尺寸不斷微縮，金屬與源極/汲極的接觸面積也持續縮小， 接觸電阻在整體電晶體的寄生電阻中所佔的比例將會持續上升。欲降低接觸電阻係 數，必須提高接面載子濃度以及降低蕭基位障接面高度。然載子濃度受限於製程溫度 及元素在基板中的固態溶解度，除非更換基板材料，不容易再提高，降低蕭基位障高 度便成為當務之急。 本三年期計畫包含四個部分：極低蕭基位障高度的參數擷取與製程技術、極低接觸 電阻係數的參數擷取與製程技術、三維物性/化性/模擬分析技術、低寄生電阻奈米電晶 體整合技術。 第一年度以建立極低蕭基位障高度以及極低接觸電阻係數的參數擷取技術為主，以 便驗證後續製程技術開發的成效。本年度並將完成蕭基位障元件製作以及接觸電阻係數 的測試結構的設計，並嘗試幾種降低蕭基位障高度的技術。第二年度將延續第一年的進 度，尋求將蕭基位障高度降低到0.4eV 以下，接觸電阻係數3 Ω-μm2 以下的材料與製程 技術，並對各種製程的調變機制進行深入的理論分析。第三年度將整合前兩年度所發展 的低蕭基位障高度以及低接觸電阻技術於奈米尺度電子元件之製作，以驗證降低接觸電 阻對於提升元件性能的作用。 本計畫可以產出蕭基位障高度低於0.4eV、接觸電阻係數低於3 Ω-μm2 的材料與製 程技術，並在30nm 以下的電晶體驗證。此計畫規格符合2007 年ITRS 預估的2016 年 需求，極具學術與產業應用價值。

With the fast scaling-down of CMOSFETs, the metal to source/drain contact area becomes small and small. Therefore, the contact resistance becomes the dominant factor of the total parasitic resistance. To reduce the contact resistance, the only two methods are to increase the carrier concentration at the contact interface and to reduce the Schottky barrier height of the metal/Si contact. However, the carrier concentration is limited by the thermal budget and the solid-state solubility, and is hard to increase except we change the substrate material. Therefore, the reduction of Schottky barrier height becomes emergency. This 3-year project consists of four parts – parameter extraction and process technology for ultra-low Schottky barrier height, parameter extraction and process technology for ultra-low contact resistivity, 3-dimentional physical/chemical/numerical analysis techniques, and low parasitic resistance nano-scale MOSFET process integration. In the first year, the main task is to develop the parameter extraction technology for ultra-low Schottky barrier height and ultra-low contact resistivity. Several potential low Shottky barrier height processes will be evaluated. We will also examine the accuracy of the existing test structures and design new test structure for ultra-low contact resistivity. In the 2nd year, we will follow the progress in the first year to develop new materials and process technologies to reduce the Schottky barrier height to <0.4eV and the contact resistivity to < 3 Ω-μm2. The mechanisms of Schottky barrier height modulation will be investigated by using three-dimensional physical/chemical/ numerical analysis. In the last year, we will integrate the low Schottky barrier height and low contact resistivity technology to fabricate low parasitic resistance nano-scale MOSFETs to verify the impact of contact resistance reduction on device performance. This project can develop materials and new technologies to achieve 0.4eV Schottky barrier height and 3 Ω-μm2 contact resistivity. These targets meet the requirements in 2016 predicted by the 2007 ITRS and have high academic and industrial application values.