Browsing by Author "McAlister, S. P."

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A 2.4/5 GHz dual-band VCO using a variable inductor and switched resonator
(2007)
Kao, H. L.
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Yang, D. Y.
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Chin, Albert
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McAlister, S. P.
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電機學院
A dual-band, low phase noise, low power and small sized voltage-controlled oscillator (VCO) with a variable inductor and switched resonator is described. The dual-band VCO operated near 2.4 GHz and 5 GHz with a phase noise of 120 and -121 dBc/Hz at a 1 MHz offset and a tuning range of 250 MHz and 1.2 GHz, respectively. The power consumption was 1.5/1.8 mW for 2.4/5 GHz operations. The total size the VCO was only 1.06 mm(2), which was achieved by using one inductor which was connected with a switch to give good dual-band operation and performance.
A CMOS-Compatible, High RF Power, Asymmetric-LDD MOSFET with Excellent Linearity
(2008)
Chang, T.
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Kao, H. L.
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Chen, Y. J.
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Liu, S. L.
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McAlister, S. P.
We report the performance of 0.18 mu m RF power MOSFETs with an Asymmetric-Lightly-Doped-Drain (LDD) design. Such devices do not have an n-type drain extension and exhibited better characteristics than conventional MOSFETs at same gate length. The devices showed a DC breakdown voltage of 6.9 V, a 0.54 W/mm power density, 115 GHz f(max), and a good adjacent channel power ratio (ACPR) linearity, as well as a 52% drain efficiency at 2.4 GHz.
A flexible organic pentacene nonvolatile memory based on high-kappa dielectric layers
(2008-12-08)
Chang, Ming-Feng
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Lee, Po-Tsung
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McAlister, S. P.
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Chin, Albert
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電子工程學系及電子研究所
We report a pentacene thin film transistor nonvolatile memory fabricated on a flexible polyimide substrate. This device shows a low program/erase voltage of 12 V, a speed of 1/100 ms, an initial memory window of 2.4 V, and a 0.78 V memory window after 48 h. This has been achieved by using a high-kappa dielectric as charge trapping, blocking, and tunneling gate insulator layers.
A low-power current-reuse LNA for ultra-wideband wireless receivers from 3.1 to 10.6 GHz
(2007)
Kao, H. L.
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Chin, Albert
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Chang, K. C.
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McAlister, S. P.
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交大名義發表
We present an ultra-wideband 3.1-10.6 GHz low-noise amplifier which uses a two-stage current-reuse structure to reduce the power. Fabricated in a 0.18 mu m CMOS process, the IC prototype achieved a power gain of 9.3 dB, a noise figure (NF) of < 5.6 dB, an input match of < -8 dB over the band, while consuming only 9.4 mW.
A program-erasable high-k Hf0.3N0.2O0.5 MIS capacitor with good retention
(2007-10-01)
Yang, H. J.
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Chin, Albert
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Chen, W. J.
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Cheng, C. F.
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Huang, W. L.
We describe a programmable-erasable MIS capacitor with a single high-kappa Hf0.3N0.2O0.5 dielectric layer. This device showed a capacitance density of similar to 6.6 fF/mu m(2), low program and erase voltages of +5 and -5 V, respectively, and a large Delta V-fb memory window of 1.5 V. In addition, the 25 degrees C data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf0.3N0.2O0.5.
Comparison of InGaAs MOSFETs with germanium-on-insulator CMOS
(2006-08-01)
Chin, Albert
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Chen, C.
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Yu, D. S.
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Kao, H. L.
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McAlister, S. P.
High mobility channel materials such as Ge and compound semiconductors (CS) show promise for future generation MOSFETs. The challenge is to integrate these materials with a Si substrate and create good interfaces in the devices. Here we show dislocation-free CSOI and Ge-on-insulator (GOI) devices with good characteristics. The InAlAs/InGaAs/InAlAs-OI on Si MESFETs shows a mobility of 8100 cm(2)/V s. To reduce the leakage current an Al2O3/InGaAs MOSFET was fabricated. Good 451 cm(2)/V S mobility was obtained, higher than the 340 cm(2)/V S of GOI MOSFETs. However the marginally better mobility than GOI and 18X lower mobility than MESFETs indicate that the soft phonon scattering, high-kappa interface scattering and process variations are challenges for CS MOSFETs. In contrast, the GOI CMOS provides a simpler process and significantly higher electron and hole mobilities than its Si counterparts. (C) 2006 Elsevier Ltd. All rights reserved.
DC-RF performance improvement for strained 0.13 mu m MOSFETs mounted on a flexible plastic substrate
(2006)
Kao, H. L.
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Chin, Albert
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Liao, C. C.
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Tseng, Y. Y.
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McAlister, S. P.
By applying 0.7% tensile strain to the flexible die of a 0.13 mu m thin-body (40 mu m) Si MOSFET mounted on plastic, both the DC and RF performance have been improved. The current I(d,sat) was 14.3% higher, and f(T) increased from 103 to 118 GHz with NF(min) decreasing from 0.89 to 0.75 dB at 10 GHz. These improvements are comparable with those for SiN-capped 90 nm strained-Si nMOS and consistent with device simulations. The approach has the advantages of better RF passive devices on the insulating plastic substrate and low cost.
Good 150 degrees C Retention and Fast Erase Characteristics in Charge-Trap-Engineered Memory having a Scaled Si3N4 Layer
(2008)
Lin, S. H.
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Chin, Albert
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Yeh, F. S.
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McAlister, S. P.
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電子工程學系及電子研究所
We report a new charge-trap-engineered flash non-volatile memory that has combined 5nm Si3N4 and 0.9nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150 degrees C under a 100 mu s and +/- 16V P/E, this device showed good device integrity of a 5.6V initial Delta V-th window and 3.8V 10-year extrapolated retention window. These data are better than the 3.3V initial Delta V-th and 1.7V 10-year data for a similar structure not having the extra WON layer.
High density and low leakage current in TiO(2) MIM capacitors processed at 300 degrees C
(2008-08-01)
Cheng, C. H.
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Lin, S. H.
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Jhou, K. Y.
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Chen, W. J.
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Chou, C. P.
We report Ir/TiO(2)/TaN metal-insulator-metal capacitors processed at only 300 degrees C, which show a capacitance density of 28 fF/mu m(2) and a leakage current of 3 x 10(-8) (25 degrees C) or 6 x 10(-7) (125 degrees C) A/cm(2) at -1 V. This performance is due to the combined effects of 300 degrees C nanocrystallized high-kappa, TiO(2), a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.
HtLaON n-MOSFETs using a low work function HfSix gate
(2007-12-01)
Cheng, C. F.
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Wu, C. H.
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Su, N. C.
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Wang, S. J.
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McAlister, S. P.
At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm(2)/(V center dot s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-degrees C rapid thermal annealing, making them fully compatible with current very large scale integration fabrication lines.
Improved high-temperature leakage in high-density MIM capacitors by using a TiLaO dielectric and an Ir electrode
(2007-12-01)
Cheng, C. H.
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Pan, H. C.
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Yang, H. J.
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Hsiao, C. N.
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Chou, C. P.
We have fabricated high-kappa. TaN/Ir/TiLaO/TaN metal-insulator-metal capacitors. A low leakage current of 6.6 x 10(-7) A/cm(2) was obtained at 125 degrees C for 24-fF/mu m(2) density capacitors. The excellent device performance is due to the combined effects of the high-kappa TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.
Improved RF Power Performance in a 0.18-mu m MOSFET Which Uses an Asymmetric Drain Design
(2008-12-01)
Chang, T.
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Kao, H. L.
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McAlister, S. P.
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Horng, K. Y.
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Chin, Albert
We have fabricated 0.18-mu m asymmetric MOSFETs using a foundry-standard 1P6M process, without making any process modifications. In comparison with a conventional 0.18-mu m MOSFET, the asymmetric MOSFET design leads to a 64% improvement in the saturated output power and 8 dB better adjacent channel power ratio. The improvement in the RF power E performance of these MOS transistors suggests that they should be suitable for medium power amplifiers.
Improvement of the performance of strained 0.13 mu m MOSFETs mounted on flexible plastic substrates
(2007)
Kao, H. L.
;
Liao, C. C.
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McAlister, S. P.
;
Chin, Albert
;
電子工程學系及電子研究所
Improvement of the performance of TiHfO MIM capacitors by using a dual plasma treatment of the lower electrode
(2008-10-01)
Cheng, C. H.
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Pan, H. C.
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Huang, C. C.
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Chou, C. P.
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Hsiao, C. N.
We show that a conventional nitrogen plasma treatment is insufficient to suppress the formation of an interfacial layer at the bottom electrode of TiHfO metal-insulator-metal (MIM) capacitors. However, the capacitance density and leakage current of TaN/TiHfO/TaN MIM capacitors monotonically improve by exposing the lower TaN electrode to an additional oxygen plasma treatment. By performing dual oxygen and nitrogen plasma treatments on the lower electrode, the leakage current was 4.8 x 10(-6) A/cm(2) (at -1 V) at a 28 fF/mu m(2) capacitance density.
Low subthreshold swing HfLaO/pentacene organic thin-film transistors
(2008-03-01)
Chang, M. R.
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Lee, P. T.
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McAlister, S. P.
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Chin, Albert
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電子工程學系及電子研究所
We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of - 1.3 V, and a field-effect mobility of 0.71 cm(2)/V.s. This occurred along with an ON-OFF state drive current ratio of 1.0 x 10(5), when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm(2) that is given by the HftaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 x 10(-7) A/cm(2) at 2 V.
Small-Subthreshold-Swing and Low-Voltage Flexible Organic Thin-Film Transistors Which Use HfLaO as the Gate Dielectric
(2009-02-01)
Chang, M. F.
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Lee, P. T.
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McAlister, S. P.
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Chin, Albert
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電子工程學系及電子研究所
Pentacene organic thin-film transistors (OTFTs) with a high-k HfLaO dielectric were integrated onto flexible polyimide substrates. The pentacene OTFTs exhibited good performance, such as a low subthreshold swing of 0.13 V/decade and a threshold voltage of -1.25 V. The field-effect mobility was 0.13 cm(2)/V . s at an operating voltage as low as only 2.5 V. These characteristics are attractive for high-switching-speed and low-power applications.
Thermal leakage improvement by using a high-work-function ni electrode in high-kappa TiHfO metal-insulator-metal capacitors
(2007)
Chiang, K. C.
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Huang, C. C.
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Pan, H. C.
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Hsiao, C. N.
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Lin, J. W.
An unavoidable drawback when using high-kappa dielectrics in capacitors is the small bandgap and the related reduction in the band-offset, which results in a large leakage current at elevated temperatures. We report improvements in the thermal leakage current by using Ni as a high-work-function top electrode for high-kappa TiHfO capacitors. This avoids sacrificing the overall kappa value by using a multilayer or laminate structure and results in better voltage linearity, which is important for analog/radio frequency integrated circuits. (c) 2007 The Electrochemical Society.
Use of a high-work-function ni electrode to improve the stress reliability of Analog SrTiO3 metal-insulator-metal capacitors
(2007-08-01)
Chiang, K. C.
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Cheng, C. H.
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Jhou, K. Y.
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Pan, H. C.
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Hsiao, C. N.
We have studied the stress reliability of low-energy-bandgap high-kappa. SrTiO3 metal-insulator-metal capacitors under constant voltage stress. By using a high-work-function Ni electrode (5.1 eV), we reduced the degrading effects of stress on the capacitance variation (Delta C/C), the quadratic voltage coefficient of capacitance (VCC-alpha), and the long-term reliability, in contrast with using a TaN. The improved stress reliability for the Ni electrode capacitors is attributed to a reduction of carrier injection and trapping.
Very low noise in 90nm node RF MOSFETs using a new layout
(2007-01-01)
Kao, H. L.
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Chin, Albert
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Liao, C. C.
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McAlister, S. P.
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電子工程學系及電子研究所
We have directly measured a record low minimum noise figure (NFmin) of 0.46 dB at 10 GM, along with a high 16.6 dB Associated Gain, in an 8-finger 90 nm node MOSFET (L-G = 65nm) without de-embedding. At 18 GHz, NFmin was 0.83 dB with 13.5 dB gain. This was achieved using a microstrip line layout to screen the RF noise generated by the lossy substrate.
Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions
(2007)
Cheng, C. F.
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Wu, C. H.
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Su, N. C.
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Wang, S. J.
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McAlister, S. P.
We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.