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顯示 21 到 33 筆資料，總共 33 筆 < 上一頁 
公開日期標題作者
1-一月-1996A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET'sLee, RGH; Su, JS; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devicesChung, SS; Liu, YR; Yeh, CF; Wu, SR; Lai, CS; Chang, TY; Ho, JH; Liu, CY; Huang, CT; Tsai, CT; Shiau, WT; Sun, SW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devicesChung, SS; Chen, SJ; Yang, WJ; Yang, JJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1999A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cyclesChung, SS; Yih, CM; Cheng, SM; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxideChung, SS; Chen, SJ; Yang, CK; Cheng, SM; Lin, SH; Sheng, YC; Lin, HS; Hung, KT; Wu, DY; Yew, TR; Chien, SC; Liou, FT; Wen, F; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003A novel leakage current separation technique in a direct Tunneling regime gate oxide SONOS memory cellChung, SS; Chiang, PY; Chou, G; Huang, CT; Chen, P; Chu, CH; Hsu, CCH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996A numerical model for simulating MOSFET gate current degradation by considering the interface state generationYih, CM; Chung, SS; Hsu, CCH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003The performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gateTsai, HW; Chiang, PY; Chung, SS; Kuo, DS; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997Performance and reliability evaluations of P-channel flash memories with different programming schemesChung, SS; Kuo, SN; Yih, CM; Chao, TS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluationChung, SS; Chen, DC; Cheng, CT; Yeh, CF; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-十一月-1997A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditionsCheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1997A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditionsCheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1999Universal switched-current integrator blocks for SI filter designChan, JL; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 21 到 33 筆資料，總共 33 筆 < 上一頁