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公開日期標題作者
2010Evaluation of Static Noise Margin and Performance of 6T FinFET SRAM Cells with Asymmetric Gate to Source/Drain Underlap DevicesHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2014Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET DevicesChen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge RoughnessChen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM CellsHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface OrientationHu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2011FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate DielectricsHu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM CellsHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic CircuitsFan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Impacts of Single Trap Induced Random Telegraph Noise on FinFET Devices and SRAM Cell StabilityFan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic CircuitsYang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic CircuitsChen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMsHsieh, Chien-Yu; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2012Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMsHsieh, Chien-Yu; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2015Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variationLee, Ko-Chun; Fan, Ming-Long; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2013Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using a Voronoi ApproachChou, Shao-Heng; Fan, Ming-Long; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2014Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer CouplingFan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電機工程學系; Department of Electrical and Computer Engineering
五月-2015Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FETHsu, Chih-Wei; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2015Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FETFan, Ming-Long; Hu, Vita Pi-Ho; Hsu, Chih-Wei; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2010Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM ModelFan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 交大名義發表; National Chiao Tung University
2013Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense AmplifiersFan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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