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公開日期標題作者
1-八月-1993ON THE DESIGN AUTOMATION OF THE MEMORY-BASED VLSI ARCHITECTURES FOR FIR FILTERSLEE, HR; JEN, CW; LIU, CM; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
1-八月-1992ON THE DESIGN OF VLSI ARRAYS FOR DISCRETE FOURIER-TRANSFORMLIU, CM; JEN, CW; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
1-十一月-1992A PARALLEL ADAPTIVE ALGORITHM FOR MOVING TARGET DETECTION AND ITS VLSI ARRAY REALIZATIONLIU, CM; JEN, CW; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1994A RASTER ENGINE FOR COMPUTER GRAPHICS AND IMAGE COMPOSITIONCHEN, CL; LIN, CH; LEE, HR; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-1990REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAYWANG, JJ; JEN, CW; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-八月-1995SCALABLE ARRAY ARCHITECTURE DESIGN FOR FULL SEARCH BLOCK MATCHINGCHANG, SF; HWANG, JH; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-1987SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUITJOU, SJ; SHEN, WZ; JEN, CW; LEE, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
12-十月-1995UNIFIED ARRAY ARCHITECTURE FOR DISCRETE COSINE TRANSFORM, SINE TRANSFORM AND THEIR INVERSESGUO, JI; CHEN, CS; JEN, CW; 電控工程研究所; Institute of Electrical and Control Engineering
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