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顯示 21 到 28 筆資料，總共 28 筆 < 上一頁 
公開日期標題作者
二月-2016Low-Leakage Tetragonal ZrO2 (EOT < 1 nm) With In Situ Plasma Interfacial Passivation on GermaniumChou, Chen-Han; Chang, Hao-Hsuan; Hsu, Chung-Chun; Yeh, Wen-Kuan; Chien, Chao-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulatorsHsieh, Ping-Yi; Chang, Yi-Jui; Chen, Pin-Jun; Chen, Chun-Liang; Yang, Chih-Chao; Huang, Po-Tsang; Chen, Yi-Jing; Shen, Chih-Ming; Liu, Yu-Wei; Huang, Chien-Chi; Tai, Ming-Chi; Lo, Wei-Chung; Shen, Chang-Hong; Shieh, Jia-Min; Chang, Da-Chiang; Chen, Kuan-Neng; Yeh, Wen-Kuan; Hu, Chenming; 交大名義發表; National Chiao Tung University
1-一月-2019Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETsHsueh, Fu-Kuo; Lee, Chun-Ying; Xue, Cheng-Xin; Shen, Chang-Hong; Shieh, Jia-Min; Chen, Bo-Yuan; Chiu, Yen-Cheng; Chen, Hsiu-Chih; Kao, Ming-Hsuan; Huang, Wen-Hsien; Li, Kai-Shin; Wu, Chien-Ting; Lin, Kun-Lin; Chen, Kun-Ming; Huang, Guo-Wei; Chang, Meng-Fan; Hu, Chenming; Yeh, Wen-Kuan; 交大名義發表; National Chiao Tung University
2016MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 AvailabilityLi, Kai-Shin; Wu, Bo-Wei; Li, Lain-Jong; Li, Ming-Yang; Cheng, Chia-Chin Kevin; Hsu, Cho-Lun; Lin, Chang-Hsien; Chen, Yi-Ju; Chen, Chun-Chi; Wu, Chien-Ting; Chen, Min-Cheng; Shieh, Jia-Min; Yeh, Wen-Kuan; Chueh, Yu-Lun; Yang, Fu-Liang; Hu, Chenming; 材料科學與工程學系; Department of Materials Science and Engineering
1-一月-2018Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and FtLi, Kai-Shin; Wei, Yun-Jie; Chen, Yi-Ju; Chiu, Wen-Cheng; Chen, Hsiu-Chih; Lee, Min-Hung; Chiu, Yu-Fan; Hsueh, Fu-Kuo; Wu, Bo-Wei; Chen, Pin-Guang; Lai, Tung-Yan; Chen, Chun-Chi; Shieh, Jia-Min; Yeh, Wen-Kuan; Salahuddin, Sayeef; Hu, Chenming; 交大名義發表; National Chiao Tung University
1-一月-2016A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FETTang, Ying-Tsan; Li, Kai-Shin; Li, Lain-Jong; Li, Ming-Yang; Lin, Chang-Hsien; Chen, Yi-Ju; Chen, Chun-Chi; Su, Chuan-Jung; Wu, Bo-Wei; Wu, Cheng-San; Chen, Min-Cheng; Shieh, Jia-Min; Yeh, Wen-Kuan; Su, Po-Cheng; Wang, Tahui; Yang, Fu-Liang; Hu, Chenming; 電機工程學系; Department of Electrical and Computer Engineering
2016Suspended Ge Gate-All-Around Nanowire nFETs with Junction Isolation on Bulk SiWan, Chia-Chen; Luo, Guang-Li; Hsu, Shu-Han; Hung, Kuo-Dong; Chu, Chun-Lin; Hou, Tuo-Hung; Su, Chun-Jun; Chen, Szu-Hung; Wu, Wen-Fa; Yeh, Wen-Kuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power TechnologyChen, Min-Cheng; Li, Kai-Shin; Li, Lain-Jong; Lu, Ang-Yu; Li, Ming-Yang; Chang, Yung-Huang; Lin, Chang-Hsien; Chen, Yi-Ju; Hou, Yun-Fang; Chen, Chun-Chi; Wu, Bo-Wei; Wu, Cheng-San; Yang, Ivy; Lee, Yao-Jen; Shieh, Jia-Min; Yeh, Wen-Kuan; Shih, Jyun-Hong; Su, Po-Cheng; Sachid, Angada B.; Wang, Tahui; Yang, Fu-Liang; Hu, Chenming; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
顯示 21 到 28 筆資料，總共 28 筆 < 上一頁