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公開日期標題作者
2013Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap DevicesHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2013Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FETFan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nein; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2012Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic CircuitsFan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2012"Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits"Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2011Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature SensitivityHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2011Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature SensitivityHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2009Analytical Quantum-Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold RegionWu, Yu-Sheng; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFETYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2012Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor StackingHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM CellsYu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2014Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETsYu, Chang-Hung; Su, Pin; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
2015Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its SuppressionYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2012A Closed-Form Quantum "Dark Space" Model for Predicting the Electrostatic Integrity of Germanium MOSFETs With High-k Gate DielectricWu, Yu-Sheng; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
七月-2016A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect TransistorsYou, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2013Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFETHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2009A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate SOI MOSFETsLee, Wei; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2011Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability-A Model-Based ApproachFan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells considering Variability and Temperature SensitivityHu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic CircuitsPao, Chia-Hao; Fan, Ming-Long; Tsai, Ming-Fu; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2009A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETsKuo, Jack Jyun-Yan; Chen, William Po-Nien; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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