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Showing results 1 to 12 of 12
Issue DateTitleAuthor(s)
1-Jul-2017Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETsHsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
2016Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC ApplicationsHsieh, Don-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
Nov-2016High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FETHsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
Feb-2017High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization techniqueHsieh, Dong-Ru; Kuo, Po-Yi; Lin, Jer-Yi; Chen, Yi-Hsuan; Chang, Tien-Shun; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
1-Oct-2015Impact of Crystallization Method on Poly-Si Tunnel FETsChen, Yi-Hsuan; Ma, William Cheng-Yu; Lin, Jer-Yi; Lin, Chun-Yen; Hsu, Po-Yang; Huang, Chi-Yuan; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2015Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold SwingKuo, Po-Yi; Lin, Jer-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2016Investigation of Hot Carrier Reliability of Ultrathin Poly-Si Nanobelt Junctionless (UTNB-JL) Transistors on Different Underlying InsulatorsChang, Jen-Hong; Chung, Chun-Chih; Lin, Jer-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-Aug-2018Junctionless FETs With a Fin Body for Multi-V-TH and Dynamic Threshold OperationKumar, Malkundi Puttaveerappa Vijay; Lin, Jer-Yi; Kao, Kuo-Hsing; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-Jan-2018Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress ReliabilityLin, Jer-Yi; Kumar, Malkundi Puttaveerappa Vijay; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
Dec-2016Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC ApplicationLin, Jer-Yi; Kuo, Po-Yi; Lin, Ko-Li; Chin, Chun-Chieh; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
1-Sep-2018Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping ConcentrationsLin, Jer-Yi; Tsai, Chan-Yi; Shen, Chiuan-Huei; Chung, Chun-Chih; Kumar, Malkundi Puttaveerappa Vijay; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-Feb-2018Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance LimitChung, Chris Chun-Chih; Shen, Chiuan-Huei; Lin, Jer-Yi; Chin, Chun-Chieh; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
Showing results 1 to 12 of 12