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Showing results 1 to 6 of 6
Issue DateTitleAuthor(s)
1-Jan-2002Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devicesWang, HCH; Wang, CC; Diaz, CH; Liew, BK; Sun, JYC; Wang, TH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-2003Bi-mode breakdown test methodology of ultrathin oxideSu, HD; Chiou, BS; Ko, CY; Wu, SY; Chang, MH; Lee, KH; Chen, YS; Chao, CP; See, YC; Sun, JYC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Sep-2003Characteristics of oxide breakdown and related impact on device of ultrathin (2.2 nm) silicon dioxideSu, HD; Chiou, BS; Wu, SY; Chang, MH; Lee, KH; Chen, YS; Cha, CP; See, YC; Sun, JYC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-2003A floating well method for exact capacitance-voltage measurement of nano technologySu, HD; Chiou, BS; Wu, SY; Chang, MH; Lee, KH; Chen, YS; Chao, CP; See, YC; Sun, JYC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-2000Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technologyWang, HCH; Diaz, CH; Liew, BK; Sun, JYC; Wang, TH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Oct-2001Improving the RF performance of 0.18 mu m CMOS with deep n-well implantationSu, JG; Hsu, HM; Wong, SC; Chang, CY; Huang, TY; Sun, JYC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 6 of 6